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general description the max5441max5444 are serial-input, voltage-out- put, 16-bit digital-to-analog converters (dacs) in tiny ?ax packages, 50% smaller than comparable dacs in 8-pin sos. they operate from low +3v (max5443/ max5444) or +5v (max5441/max5442) single sup- plies. they provide 16-bit performance (?lsb inl and ?lsb dnl) over temperature without any adjustments. unbuffered dac outputs result in a low supply current of 120? and a low offset error of 2lsb. the dac output ranges from 0 to v ref . for bipolar operation, matched scaling resistors are provided in the max5442/max5444 for use with an external preci- sion op amp (such as the max400), generating a ? ref output swing. a 16-bit serial word is used to load data into the dac latch. the 25mhz, 3-wire serial interface is compatible with spi/qspi/microwire, and can interface directly with optocouplers for applications requiring isolation. a power-on reset circuit clears the dac output to code 0 (max5441/max5443) or code 32768 (max5442 /max5444) when power is initially applied. a logic low on clr asynchronously clears the dac out- put to code 0 (max5441/max5443) or code 32768 (max5442/max5444) independent of the serial interface. the max5441/max5443 are available in 8-pin ?ax packages. the max5442/max5444 are available in 10- pin ?ax packages. applications high-resolution offset and gain adjustment industrial process control automated test equipment data-acquisition systems features ultra-small 3mm x 5mm 8-pin max package low 120 a supply current fast 1 s settling time 25mhz spi/qspi/microwire-compatible serial interface v ref range extends to v dd +5v (max5441/max5442) or +3v (max5443/max5444) single-supply operation full 16-bit performance without adjustments unbuffered voltage output directly drives 60k ? loads power-on reset circuit clears dac output to code 0 (max5441/max5443) or code 32768 (max5442/max5444) schmitt-trigger inputs for direct optocoupler interface asynchronous clr max5441?ax5444 +3v/+5v, serial-input, voltage-output, 16-bit dacs ________________________________________________________________ maxim integrated products 1 10 9 8 7 6 1 2 3 4 5 gnd v dd rfb inv din sclk cs ref top view max5442 max5444 out clr max-8 out sclk cs 1 + + 2 8 7 v dd din ref max5441 max5443 3 4 6 5 max-10 gnd clr pin configurations 19-1846; rev 3; 1/09 ordering information ?ax is a registered trademark of maxim integrated products, inc. qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor corp. part temp range pin-package inl (lsb) supply (v) max5441 acua+ 0 c to +70 c 8 ?ax ? 5 max5441aeua+ -40 c to +85 c 8 ?ax 25 max5441bcua+ 0 c to +70 c 8 ?ax 45 max5441beua+ -40 c to +85 c 8 ?ax ? 5 max5442 acub+ 0 c to +70 c 10 ?ax 25 max5442aeub+ -40 c to +85 c 10 ?ax ? 5 max5442bcub+ 0 c to +70 c 10 ?ax 45 max5442beub+ -40 c to +85 c 10 ?ax ? 5 functional diagrams appear at end of data sheet. ordering information continued at end of data sheet. for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available + denotes a lead(pb)-free/rohs-compliant package. note: for leaded version, contact factory.
max5441?ax5444 +3v/+5v, serial-input, voltage-output, 16-bit dacs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +3v (max5443/max5444) or +5v (max5441/max5442), v ref = +2.5v, c l = 10pf, gnd = 0, r l = , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v cs , sclk, din, clr to gnd ...................................-0.3v to +6v ref to gnd ................................................-0.3v to (v dd + 0.3v) out, inv to gnd .....................................................-0.3v to v dd rfb to inv ...................................................................-6v to +6v rfb to gnd.................................................................-6v to +6v maximum current into any pin ...........................................50ma continuous power dissipation (t a = +70?) 8-pin ?ax (derate 4.5mw/? above +70?)...............362mw 10-pin max (derate 5.6mw/? above +70?) ..............444mw operating temperature ranges max544 _ _cu_ ...................................................0? to +70? max544 _ _eu_.................................................-40? to +85? storage temperature range .............................-65? to +150? maximum die temperature..............................................+150? lead temperature (soldering, 10s) .................................+300? bipolar mode unipolar mode (note 3) (note 2) conditions k ? 6 r ref reference input resistance (note 4) 10 v 2.0 v dd v ref reference input range power-supply rejection ppm/? ?.5 bzs tc bipolar zero tempco lsb ?.015 bipolar resistor matching 1 r out dac output resistance k ? 6.2 bits 16 n resolution ppm/? ?.1 gain-error tempco lsb gain error (note 1) ppm/? ?.05 zs tc zero-code tempco integral nonlinearity units min typ max symbol parameter max544_a lsb bipolar zero offset error (note 5) 15 v/? sr voltage-output slew rate dynamic performance?nalog section to 1 / 2 lsb of fs 1 ? output settling time % guaranteed monotonic lsb ?.5 ? dnl differential nonlinearity inl r fb /r inv ratio error ?0 lsb ? +2.7v v dd +3.3v (max5443/max5444) psr +4.5v v dd +5.5v (max5441/max5442) ? major-carry transition 7 nv-s dac glitch impulse code = 0000 hex; cs = v dd ; sclk, din = 0 to v dd levels 0.2 nv-s digital feedthrough ?.5 ? ?0 zse lsb ? zero-code offset error ?.5 ? max544_b static performance?nalog section reference input
max5441?ax5444 +3v/+5v, serial-input, voltage-output, 16-bit dacs _______________________________________________________________________________________ 3 timing characteristics (v dd = +2.7v to +3.3v (ma5443/max5444) , v dd = +4.5v to +5.5v (max5441/max5442), v ref = +2.5v, gnd = 0, cmos inputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (figure 1) note 1: gain error tested at v ref = +2.0v, +2.5v, and +3.0v (max5443/max5444) or v ref = +2.0v, +2.5v, +3.0v, and +5.5v (max5441/ max5442). note 2: r out tolerance is typically ?0%. note 3: min/max range guaranteed by gain-error test. operation outside min/max limits will result in degraded performance. note 4: reference input resistance is code-dependent, minimum at 8555hex in unipolar mode, 4555hex in bipolar mode. note 5: slew-rate value is measured from 10% to 90%. note 6: guaranteed by design. not production tested. note 7: guaranteed by power-supply rejection test and timing characteristics . all digital inputs at v dd or gnd all digital inputs at v dd or gnd max5443/max5444 code = 0000 hex, v ref = 1v p-p at 100khz code = 0000 hex code = ffff hex (note 6) conditions mw 0.36 pd power dissipation ma 0.12 0.20 i dd positive supply current v 2.7 3.6 v dd positive supply range (note 7) v 0.15 v h hysteresis voltage pf 310 c in input capacitance mv p-p 1 ? ? i in input current v 0.8 v il input low voltage v 2.4 v ih input high voltage reference feedthrough db 92 snr signal-to-noise ratio 70 pf 170 c inref reference input capacitance units min typ max symbol parameter (note 6) conditions ? 20 v dd high to cs low (power-up delay) ns 20 t cl sclk pulse width low ns 20 t ch mhz 25 f clk sclk frequency sclk pulse width high ns 20 t clw clr pulse width low ns 0 t dh din to sclk high hold ns 15 t ds din to sclk high setup ns 15 t css0 cs low to sclk high setup ns 15 t css1 cs high to sclk high setup ns 35 t csh0 sclk high to cs low hold ns 20 t csh1 sclk high to cs high hold units min typ max symbol parameter code = ffff hex mhz 1 bw reference -3db bandwidth max5441/max5442 4.5 5.5 0.60 dynamic performance?eference section static performance?igital inputs power supply max5441/max5442 max5443/max5444 electrical characteristics (continued) (v dd = +3v (max5443/max5444) or +5v (max5441/max5442), v ref = +2.5v, c l = 10pf, gnd = 0, r l = , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.)
max5441?ax5444 +3v/+5v, serial-input, voltage-output, 16-bit dacs 4 _______________________________________________________________________________________ __________________________________________typical operating characteristics (v dd = +3v (max5443/max5444) or +5v (max5441/max5442), v ref = +2.5v, gnd = 0, r l = , t a = t min to t max , unless other- wise noted. typical values are at t a = +25?.) 0 0.050 0.025 0.100 0.075 0.125 0.150 -40 10 -15 356085 supply current vs. temperature max5441/44 toc01 temperature ( c) suuply current (ma) v dd = +5v v dd = +3v 0.05 0.09 0.08 0.06 0.10 0.11 0.12 02.0 1.5 0.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 supply current vs. reference voltage max5441/44 toc02 reference voltage (v) supply current (ma) 0.07 v dd = +5v 0.05 0.07 0.06 0.09 0.08 0.11 0.10 0.12 0 1.0 1.5 0.5 2.0 2.5 3.0 supply current vs. reference voltage max5441/44 toc03 reference voltage (v) supply current (ma) v dd = +3v -0.2 0 -0.1 0.2 0.1 0.3 0.4 -40 10 -15 356085 zero-code offset error vs. temperature max5441/44 toc04 temperature ( c) offset error (lsb) -0.4 0 -0.2 0.4 0.2 0.6 0.8 -40 10 -15 356085 integral nonlinearity vs. temperature max5441/44 toc05 temperature ( c) inl (lsb) +inl -inl -0.4 -0.2 -0.3 0 -0.1 0.1 0.2 -40 10 -15 356085 differential nonlinearity vs. temperature max5441/44 toc06 temperature ( c) dnl (lsb) +dnl -dnl -0.30 -0.20 -0.25 -0.10 -0.15 -0.05 0 -40 10 -15 356085 gain error vs. temperature max5441/44 toc07 temperature ( c) gain error (lsb) 0.25 0.20 0.15 0.10 0.05 -0.05 -0.10 -0.15 -0.20 -0.25 0 0 15k 5k 25k 35k 45k 55k 66k integral nonlinearity vs. code max5441/44 toc08 code inl (lsb) 0.125 0.100 0.075 0.050 0.025 -0.025 -0.050 -0.075 -0.100 -0.125 0 0 15k 5k 25k 35k 45k 55k 66k differential nonlinearity max5441/44 toc09 code dnl (lsb)
max5441?ax5444 unipolar power-on glitch (ref = v dd ) max5441/44 toc17 50ms/div v dd 2v/div v out 10mv/div +3v/+5v, serial-input, voltage-output, 16-bit dacs _______________________________________________________________________________________ 5 0 40 20 80 60 120 100 140 0 20000 30000 10000 40000 50000 60000 70000 reference current vs. digital input code max5441/44 toc10 code reference current ( a) full-scale step response (falling) 400ns/div cs 2v/div a out 1v/div c l = 20pf max5441/44 toc11 full-scale step response (rising) max5441/44 toc12 400ns/div cs 2v/div a out 1v/div c l = 20pf major-carry glitch (rising) max5441/44 toc13 200ns/div cs 1v/div a out 20mv/div c l = 20pf 0.40 0.50 0.45 0.60 0.55 0.65 0.70 2.0 3.0 3.5 2.5 4.0 4.5 5.0 integral nonlinearity vs. reference voltage max5441/44 toc16 reference voltage (v) inl (lsb) major-carry glitch (falling) max5441/44 toc14 200ns/div cs 1v/div a out 20mv/div c l = 20pf digital feedthrough max5441/44 toc15 50ns/div d in 2v/div a out 10mv/div c l = 112pf typical operating characteristics (continued) (v dd = +3v (max5443/max5444) or +5v (max5441/max5442), v ref = +2.5v, gnd = 0, r l = , t a = t min to t max , unless other- wise noted. typical values are at t a = +25?.)
max5441?ax5444 +3v/+5v, serial-input, voltage-output, 16-bit dacs 6 _______________________________________________________________________________________ pin description t csho t ch t csso t cl t dh t ds t csh1 t css1 cs sclk din d15 d14 d0 figure 1. timing diagram pin max5441 max5443 max5442 max5444 name function 1 1 ref voltage reference input 22 cs chip-select input 3 3 sclk serial clock input. duty cycle must be between 40% and 60%. 4 4 din serial data input 55 clr clear input. logic low asynchronously clears the dac to code 0 (max5441/max5443) or code 32768 (max5442/max5444). 6 6 out dac output voltage 7 inv junction of internal scaling resistors. connect to external op amp? inverting input in bipolar mode. 8 rfb feedback resistor. connect to external op amp? output in bipolar mode. 79v dd supply voltage. use +3v for max5443/max5444 and +5v for max5441/max5442. 8 10 gnd ground
max5441?ax5444 +3v/+5v, serial-input, voltage-output, 16-bit dacs _______________________________________________________________________________________ 7 detailed description the max5441?ax5444 voltage-output, 16-bit digital- to-analog converters (dacs) offer full 16-bit perfor- mance with less than 2lsb integral linearity error and less than 1lsb differential linearity error, thus ensuring monotonic performance. serial data transfer minimizes the number of package pins required. the max5441?ax5444 are composed of two matched dac sections, with a 12-bit inverted r-2r dac forming the 12 lsbs and the four msbs derived from 15 identically matched resistors. this architecture allows the lowest glitch energy to be transferred to the dac output on major-carry transitions. it also lowers the dac output impedance by a factor of eight compared max5442 max5444 max400 gnd (gnd) v dd r inv r fb rfb inv out clr sclk din cs 0.1 f +3v/+5v external op amp mc68xxxx pcs0 mosi sclk ic1 bipolar out +5v -5v 0.1 f +2.5v 1 f max6166 figure 2b. typical operating circuit?ipolar output max5441 max5442 max5443 max5444 max495 (gnd) v dd ref out sclk din cs gnd 0.1 f 0.1 f +2.5v external op amp mc68xxxx pcs0 mosi sclk unipolar out clr 1 f ic1 max6166 +3v/+5v figure 2a. typical operating circuit?nipolar output
max5441?ax5444 +3v/+5v, serial-input, voltage-output, 16-bit dacs 8 _______________________________________________________________________________________ to a standard r-2r ladder, allowing unbuffered opera- tion in medium-load applications. the max5442/max5444 provide matched bipolar offset resistors, which connect to an external op amp for bipo- lar output swings (figure 2b). digital interface the max5441?ax5444 digital interface is a standard 3-wire connection compatible with spi/qspi/ microwire interfaces. the chip-select input ( cs) frames the serial data loading at the data-input pin (din). immediately following cs ? high-to-low transition, the data is shifted synchronously and latched into the input register on the rising edge of the serial clock input (sclk). after 16 data bits have been loaded into the serial input register, it transfers its contents to the dac latch on cs ? low-to-high transition (figure 3). note that if cs is not kept low during the entire 16 sclk cycles, data will be corrupted. in this case, reload the dac latch with a new 16-bit word. clearing the dac a 20ns (min) logic-low pulse on clr asynchronously clears the dac buffer to code 0 in the max5441/ max5443 and to code 32768 in the max5442/ max5444. external reference the max5441?ax5444 operate with external voltage references from 2v to v dd . the reference voltage determines the dac? full-scale output voltage. power-on reset the power-on reset circuit sets the output of the max5441/max5443 to code 0 and the output of the max5442/max5444 to code 32768 when v dd is first applied. this ensures that unwanted dac output volt- ages will not occur immediately following a system power-up, such as after a loss of power. applications information reference and ground inputs the max5441?ax5444 operate with external voltage references from 2v to v dd , and maintain 16-bit perfor- mance if certain guidelines are followed when selecting and applying the reference. ideally, the reference? temperature coefficient should be less than 0.1ppm/? to maintain 16-bit accuracy to within 1lsb over the -40? to +85? extended temperature range. since this converter is designed as an inverted r-2r volt- age-mode dac, the input resistance seen by the voltage reference is code-dependent. in unipolar mode, the worst-case input-resistance variation is from 11.5k ? (at code 8555hex) to 200k ? (at code 0000hex). the maxi- mum change in load current for a 2.5v reference is 2.5v / 11.5k ? = 217?; therefore, the required load regulation is 7ppm/ma for a maximum error of 0.1lsb. this implies a reference output impedance of less than 18m ? . in addition, the impedance of the signal path from the volt- age reference to the reference input must be kept low because it contributes directly to the load-regulation error. the requirement for a low-impedance voltage reference is met with capacitor bypassing at the reference inputs and ground. a 0.1? ceramic capacitor with short leads between ref and gnd provides high-frequency bypassing. a surface-mount ceramic chip capacitor is preferred because it has the lowest inductance. an cs sclk din msb lsb d15 d8 d7 d6 d5 d4 d3 d2 d1 d0 sub-bits dac updated d14 d13 d12 d11 d10 d9 figure 3. max5441?ax5444 3-wire interface timing diagram
max5441?ax5444 +3v/+5v, serial-input, voltage-output, 16-bit dacs _______________________________________________________________________________________ 9 additional 1? between ref and gnd provides low-fre- quency bypassing. a low-esr tantalum, film, or organic semiconductor capacitor works well. leaded capaci- tors are acceptable because impedance is not as criti- cal at lower frequencies. the circuit can benefit from even larger bypassing capacitors, depending on the stability of the external reference with capacitive loading. unbuffered operation unbuffered operation reduces power consumption as well as offset error contributed by the external output buffer. the r-2r dac output is available directly at out, allowing 16-bit performance from +v ref to gnd without degradation at zero-scale. the dac? output impedance is also low enough to drive medium loads (r l > 60k ? ) without degradation of inl or dnl; only the gain error is increased by externally loading the dac output. external output buffer amplifier the requirements on the external output buffer amplifier change whether the dac is used in the unipolar or bipo- lar mode of operation. in unipolar mode, the output amplifier is used in a voltage-follower connection. in bipolar mode (max5442/max5444 only), the amplifier operates with the internal scaling resistors (figure 2b). in each mode, the dac? output resistance is constant and is independent of input code; however, the output ampli- fier? input impedance should still be as high as possible to minimize gain errors. the dac? output capacitance is also independent of input code, thus simplifying stability requirements on the external amplifier. in bipolar mode, a precision amplifier operating with dual power supplies (such as the max400) provides the ? ref output range. in single-supply applications, precision amplifiers with input common-mode ranges including gnd are available; however, their output swings do not normally include the negative rail (gnd) without significant degradation of performance. a sin- gle-supply op amp, such as the max495, is suitable if the application does not use codes near zero. since the lsbs for a 16-bit dac are extremely small (38.15? for v ref = 2.5v), pay close attention to the external amplifier? input specification. the input offset voltage can degrade the zero-scale error and might require an output offset trim to maintain full accuracy if the offset voltage is greater than 1/2lsb. similarly, the input bias current multiplied by the dac output resis- tance (typically 6.25k ? ) contributes to the zero-scale error. temperature effects also must be taken into con- sideration. over the -40? to +85? extended tempera- ture range, the offset voltage temperature coefficient (referenced to +25?) must be less than 0.24?/? to add less than 1/2lsb of zero-scale error. the external amplifier? input resistance forms a resistive divider with the dac output resistance, which results in a gain error. to contribute less than 1/2lsb of gain error, the input resistance typically must be greater than: the settling time is affected by the buffer input capaci- tance, the dac? output capacitance, and pc board capacitance. the typical dac output voltage settling time is 1? for a full-scale step. settling time can be sig- nificantly less for smaller step changes. assuming a single time-constant exponential settling response, a full-scale step takes 12 time constants to settle to within 1/2lsb of the final output voltage. the time constant is equal to the dac output resistance multiplied by the total output capacitance. the dac output capacitance is typically 10pf. any additional output capacitance will increase the settling time. the external buffer amplifier? gain-bandwidth product is important because it increases the settling time by adding another time constant to the output response. the effective time constant of two cascaded systems, each with a single time-constant response, is approxi- mately the root square sum of the two time constants. the dac output? time constant is 1? / 12 = 83ns, ignoring the effect of additional capacitance. if the time constant of an external amplifier with 1mhz bandwidth is 1 / 2 (1mhz) = 159ns, then the effective time con- stant of the combined system is: this suggests that the settling time to within 1/2lsb of the final output voltage, including the external buffer amplifier, will be approximately 12 180ns = 2.15?. digital inputs and interface logic the digital interface for the 16-bit dac is based on a 3-wire standard that is compatible with spi, qspi, and microwire interfaces. the three digital inputs ( cs , din, and sclk) load the digital input data serially into the dac. a 20ns (min) logic-low pulse on clr clears the data in the dac buffer. all of the digital inputs include schmitt-trigger buffers to accept slow-transition interfaces. this means that opto- couplers can interface directly to the max5441 max5444 without additional external logic. the digital inputs are compatible with ttl/cmos-logic levels. 83ns 159ns 180ns 22 () + () ? ? ? ? ? ? = 6.25k m ?? = 2 819 17
max5441?ax5444 +3v/+5v, serial-input, voltage-output, 16-bit dacs 10 ______________________________________________________________________________________ unipolar configuration figure 2a shows the max5441?ax5444 configured for unipolar operation with an external op amp. the op amp is set for unity gain, and table 1 lists the codes for this circuit. the bipolar max5442/max5444 can also be used in unipolar configuration by connecting rfb and inv to ref. this allows the dac to power-up to mid- scale. bipolar configuration figure 2b shows the max5442/max5444 configured for bipolar operation with an external op amp. the op amp is set for unity gain with an offset of -1/2v ref . table 2 lists the offset binary codes for this circuit. power-supply bypassing and ground management bypass v dd with a 0.1? ceramic capacitor connected between v dd and gnd. mount the capacitor with short leads close to the device (less than 0.25 inches). table 1. unipolar code table table 2. bipolar code table 0 0000 0000 0000 0000 v ref (1 / 65,536) 0000 0000 0000 0001 v ref (32,768 / 65,536) = 1/ 2 v ref 1000 0000 0000 0000 v ref (65,535 / 65,536) 1111 1111 1111 1111 analog output, v out msb lsb dac latch contents -v ref (32,768 / 32,768) = -v ref 0000 0000 0000 0000 -v ref (1 / 32,768) 0111 1111 1111 1111 0 1000 0000 0000 0000 +v ref (1 / 32,768) 1000 0000 0000 0001 +v ref (32,767 / 32,768) 1111 1111 1111 1111 analog output, v out msb lsb dac latch contents
max5441?ax5444 +3v/+5v, serial-input, voltage-output, 16-bit dacs ______________________________________________________________________________________ 11 _____________________ chip information process: bicmos gnd v dd out clr din sclk cs ref max5441 max5443 16-bit dac control logic 16-bit data latch serial input register gnd v dd out clr din sclk cs ref 16-bit dac control logic 16-bit data latch serial input register rfb inv max5442 max5444 functional diagrams ordering infor mation (continued) part temp range pin-package inl (lsb) supply (v) max5443 acua+ 0 c to +70 c 8 ?ax 23 max5443aeua+ -40 c to +85 c 8 ?ax ? 3 max5443bcua+ 0 c to +70 c 8 ?ax 43 max5443beua+ -40 c to +85 c 8 ?ax ? 3 max5444 acub+ 0 c to +70 c 10 ?ax 23 max5444aeub+ -40 c to +85 c 10 ?ax ? 3 max5444bcub+ 0 c to +70 c 10 ?ax 43 max5444beub+ -40 c to +85 c 10 ?ax ? 3 + denotes a lead(pb)-free/rohs-compliant package. note: for leaded version, contact factory. package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 ?ax u8+1 21-0036 90-0092 10 ?ax u10+2 21-0061 90-0330
max5441?ax5444 +3v/+5v, serial-input, voltage-output, 16-bit dacs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/00 initial release 2 10/07 changed timing diagram 6 3 1/09 added lead-free notation in ordering information . 1, 11

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